ISL6439EVAL1【PDF 10/15 页】EVALUATION BOARD 1 ISL6439

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6页 7页 8页 9页 [10页]11页 12页 13页 14页

ISL6439, ISL6439A

the modulator is simply the input voltage (V IN ) divided by the

peak-to-peak oscillator voltage Δ V OSC .

Compensation Break Frequency Equations

F Z1 = ----------------------------------

F P1 = ---------------------------------------------------------

2 π x R 2 x ? ---------------------- ?

OSC

PWM

COMPARATOR

DRIVER

V IN

L O

V OUT

1

2 π × R 2 × C 2

1

? C 1 x C 2 ?

? C 1 + C 2 ?

F Z2 = -------------------------------------------------------

F P2 = ------------------------------------

Δ V OSC

-

+

DRIVER

PHASE

C O

ESR

1

2 π x ( R 1 + R 3 ) x C 3

1

2 π x R 3 x C 3

Z FB

V E/A

-

+

ERROR

AMP

Z IN

REFERENCE

(PARASITIC)

(EQ. 5)

Figure 6 shows an asymptotic plot of the DC/DC converter’s

gain vs frequency. The actual Modulator Gain has a high gain

peak due to the high Q factor of the output filter and is not

shown in Figure 6. Using the above guidelines should give a

DETAILED COMPENSATION COMPONENTS

Compensation Gain similar to the curve plotted. The open

C 2

C 1

R 2

Z FB

C 3

Z IN

R 3

V OUT

loop error amplifier gain bounds the compensation gain.

Check the compensation gain at F P2 with the capabilities of

the error amplifier. The Closed Loop Gain is constructed on

the graph of Figure 6 by adding the Modulator Gain (in dB) to

COMP

-

+

FB

R 1

the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the

compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks

ISL6439

REFERENCE

Z FB and Z IN to provide a stable, high bandwidth (BW) overall

loop. A stable control loop has a gain crossing with

FIGURE 5. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

Modulator Break Frequency Equations

F LC = ------------------------------------------

F ESR = -------------------------------------------

? V IN ?

1

2 π x L O x C O

1

2 π x ESR x C O

(EQ. 4)

100

80

60

F Z1

F Z2

F P1

F P2

OPEN LOOP

ERROR AMP GAIN

20 log ? ---------------- ?

? V OSC ?

The compensation network consists of the error amplifier

(internal to the ISL6439) and the impedance networks Z IN

and Z FB . The goal of the compensation network is to provide

40

20

COMPENSATION

GAIN

20 log ? -------- ?

a closed loop transfer function with the highest 0dB crossing

frequency (f 0dB ) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f 0dB and

180 degrees. The expressions in Equation 5 relate the

compensation network’s poles, zeros and gain to the

0

-20

-40

R2

? R1 ?

MODULATOR

GAIN

F LC

F ESR

LOOP GAIN

components (R 1 , R 2 , R 3 , C 1 , C 2 , and C 3 ) in Figure 5. Use

-60

10

100

1K

10K

100K

1M

10M

these guidelines for locating the poles and zeros of the

compensation network:

1. Pick gain (R 2 /R 1 ) for desired converter bandwidth.

2. Place first zero below filter’s double pole (~75% F LC ).

3. Place second zero at filter ’s double pole.

4. Place first pole at the ESR zero.

5. Place second pole at half the switching frequency.

6. Check gain against error amplifier ’s open-loop gain.

7. Estimate phase margin - repeat if necessary.

10

FREQUENCY (Hz)

FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

Component Selection Guidelines

Charge Pump Capacitor Selection

A capacitor across pins CT1 and CT2 is required to create

the proper bias voltage for the ISL6439 when operating the

IC from 3.3V. Selecting the proper capacitance value is

important so that the bias current draw and the current

required by the MOSFET gates do not overburden the

FN9057.5

November 5, 2008

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